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cy2xp311 312.5 mhz lvpecl clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-59931 rev. *c revised april 7, 2014 312.5 mhz lvpecl clock generator features one lvpecl output pair output frequency: 312.5 mhz external crystal frequency: 25 mhz low rms phase jitter at 312.5 mhz, using 25-mhz crystal (1.875 mhz to 20 mhz): 0.3 ps (typical) pb-free 8-pin tssop package supply voltage: 3.3 v or 2.5 v commercial and industrial temperature ranges functional description the cy2xp311 is a pll (phase locked loop) based high performance clock generator. it is optimized to generate 10 gb ethernet, sonet, and other high performance clock frequencies. it also produces an output frequency that is 12.5 times the crystal frequency. it uses cypress?s low noise vco technology to achieve 0.3 ps typical rms phase jitter, which meets both 10 gb ethernet and sonet jitter requirements. the cy2xp311 has a crystal oscillator interface input and one lvpecl output pair. /2 phase detector crystal oscillator vco /25 oe external crystal xout xin clk clk# logic block diagram
cy2xp311 document number: 001-59931 rev. *c page 2 of 14 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 frequency table ............................................................... 3 absolute maximum conditions ....................................... 4 operating conditions ....................................................... 4 dc electrical characteristics .......................................... 5 ac electrical characteristics .......................................... 6 recommended crystal specifications ........................... 6 parameter measurements ................................................ 7 application information ................................................... 9 power supply filtering techni ques ............................. 9 termination for lvpecl output ........... .............. ......... 9 crystal input interface ......... .............. .............. ............ 9 ordering information ...................................................... 10 ordering code definitions ..... .................................... 10 package drawing and dimensions ............................... 11 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc? solutions ...................................................... 14 cypress developer community ................................. 14 technical support ................. .................................... 14
cy2xp311 document number: 001-59931 rev. *c page 3 of 14 pinouts figure 1. 8-pin tssop pinout 1 2 36 7 8 xout xin oe vss vdd clk# 45 vdd clk pin definitions 8-pin tssop pin number pin name i/o type description 1, 8 vdd power 3.3 v or 2.5 v power supply. 2 vss power ground 3, 4 xout, xin xtal output and input pa rallel resonant crystal interface 5 oe cmos input output enable. when high, the out put is enabled. when low, the output is high impedance 6, 7 clk#, clk lvpecl out put differential clock output frequency table input output frequency (mhz) crystal frequency (mhz) pll multiplier value 25 12.5 312.5
cy2xp311 document number: 001-59931 rev. *c page 4 of 14 absolute maximum conditions parameter description conditions min max unit v dd supply voltage ? ?0.5 4.4 v v in [1] input voltage, dc relative to v ss ?0.5 v dd + 0.5 v t s temperature, storage non operating ?65 150 ? c t j temperature, junction ? ? 135 ? c esd hbm esd protection, human body model jedec std 22-a114-b 2000 ? v ul?94 flammability rating at 1/8 in. v?0 ? ja [2] thermal resistance, junction to ambient 0 m/s airflow 100 ? c/w 1 m/s airflow 91 2.5 m/s airflow 87 operating conditions parameter description min max unit v dd 3.3 v supply voltage 3.135 3.465 v 2.5 v supply voltage 2.375 2.625 v t a ambient temperature, commercial 0 70 ? c ambient temperature, industrial ?40 85 ? c t pu power up time for all v dd to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms notes 1. the voltage on any input or i/o pin cannot exceed the power pin during power up. 2. simulated using apache sentinel ti software. the board is deri ved from the jedec multilayer standard. it measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). the internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. no vias are i ncluded in the model.
cy2xp311 document number: 001-59931 rev. *c page 5 of 14 dc electrical characteristics parameter description test conditions min typ max unit i dd operating supply current with output unterminated v dd = 3.465 v, oe = v dd , output unterminated ? ? 125 ma v dd = 2.625 v, oe = v dd , output unterminated ? ? 120 ma i ddt operating supply current with output terminated v dd = 3.465 v, oe = v dd , output terminated ? ? 150 ma v dd = 2.625 v, oe = v dd , output terminated ? ? 145 ma v oh lvpecl output high voltage v dd = 3.3 v or 2.5 v, r term = 50 ? to v dd ? 2.0 v v dd ? 1.15 ? v dd ? 0.75 v v ol lvpecl output low voltage v dd = 3.3 v or 2.5 v, r term = 50 ? to v dd ? 2.0 v v dd ? 2.0 ? v dd ? 1.625 v v od1 lvpecl peak-to-peak output voltage swing v dd = 3.3 v or 2.5 v, r term = 50 ? to v dd ? 2.0 v 600 ? 1000 mv v od2 lvpecl output voltage swing (v oh ? v ol ) v dd = 2.5 v, r term = 50 ? to v dd ? 1.5 v 500 ? 1000 mv v ocm lvpecl output common mode voltage (v oh + v ol )/2 v dd = 2.5 v, r term = 50 ? to v dd ? 1.5 v 1.2 ? ? v i oz lvpecl output leak age current output off, oe = v ss ?35 ? 35 ? a v ih input high voltage, oe pin ? 0.7 v dd ?v dd + 0.3 v v il input low voltage, oe pin ? ?0.3 ? 0.3 v dd v i ih input high current, oe pin oe = v dd ??115a i il input low current, oe pin oe = v ss ?50 ? ? a c in [3] input capacitance, oe pin ? ? 15 ? pf c inx [3] pin capacitance, xin & xout ? ? 4.5 ? pf notes 3. not 100% tested, guaranteed by design and characterization.
cy2xp311 document number: 001-59931 rev. *c page 6 of 14 ac electrical characteristics parameter [4] description conditions min typ max unit f out output frequency ? 312.5 ? mhz t r , t f [5] output rise or fall time 20% to 80% of full output swing ? 0.5 1.0 ns t jitter( ? ) [6] rms phase jitter (random) 312.5 mhz, (1.875 to 20 mhz) ? 0.3 ? ps t dc [7] output duty cycle measured at zero crossing point 45 ? 55 % t ohz output disable time time from falling edge on oe to stopped outputs (asynchronous) ? ? 100 ns t oe output enable time time from rising edge on oe to outputs at a valid frequency (asynchronous) ? ? 100 ns t lock startup time time for clk to reach valid frequency measured from the time v dd = v dd (min.) ? ? 5 ms recommended crystal specifications parameter [8] description min max unit mode mode of oscillation fundamental ? f frequency 25 25 mhz esr equivalent series resistance ? 50 ? c s shunt capacitance ? 7 pf notes 4. not 100% tested, guaranteed by design and characterization. 5. refer to figure 5 on page 7 . 6. refer to figure 6 on page 7 . 7. refer to figure 7 on page 8 . 8. characterized using an 18 pf parallel resonant crystal.
cy2xp311 document number: 001-59931 rev. *c page 7 of 14 parameter measurements figure 2. 3.3 v output load ac test circuit figure 3. 2.5 v output load ac test circuit figure 4. output dc parameters figure 5. output rise and fall time figure 6. rms phase jitter scope v dd v ss lvpecl 50 ? 50 ? z = 50 ? z = 50 ? clk# clk 2v -1.3v +/- 0.165v scope v dd v ss lvpecl 50 ? 50 ? z = 50 ? z = 50 ? clk# clk 2v -0.5v +/- 0.125v clk v a v b clk# v od v ocm = (v a + v b )/2 20% 80% t r clk 20% 80% clk# t f
cy2xp311 document number: 001-59931 rev. *c page 8 of 14 figure 7. output duty cycle figure 8. output enable timing parameter measurements (continued) phase noise phase noise mask offset frequency f1 f2 rms jitter = area under the masked phase noise plot noise power clk t pw t period t dc = t pw t period clk# oe clk high impedance t ohz t oe v il v ih clk#
cy2xp311 document number: 001-59931 rev. *c page 9 of 14 application information power supply filtering techniques as in any high speed analog circuitry, noise at the power supply pins can degrade performance. to achieve optimum jitter performance, use good power supply isolation practices. figure 9 illustrates a typical filtering scheme. 0.01 to 0.1 f ceramic chip capacitors are located close to the vdd pins to provide a short and low impedance ac path to ground. a 1 to 10 f ceramic or tantalum capacitor is located in the general vicinity of this device and may be shared with other devices. an acceptable alternative power supply configuration is shown in figure 10 . figure 9. power supply filtering figure 10. alternative power supply filtering termination for lvpecl output the cy2xp311 implements its lvpecl driver with a current steering design. for proper operation, it requires a 50 ohm dc termination on each of the two output signals. for 3.3 v operation, this data sheet specifies output levels for termination to v dd ?2.0 v. this same termination voltage can also be used for v dd = 2.5 v operation, or it can be terminated to v dd ?1.5 v. note that it is also possible to terminate with 50 ohms to ground (v ss ), but the high and low signal levels differ from the data sheet values. termination resistors are best located close to the destination device. to avoid reflections, trace characteristic impedance (z 0 ) should match the termination impedance. figure 11 shows a standard termination scheme. figure 11. lvpecl output termination crystal input interface the cy2xp311 is characterized with 18 pf parallel resonant crystals. the capacitor values shown in figure 12 are determined using a 25 mhz 18 pf parallel resonant crystal and are chosen to minimize the ppm error. note that the optimal values for c1 and c2 depend on the parasitic trace capacitance and are therefore layout dependent. figure 12. crystal input interface 3.3v or 2.5v 0. 01f vdd (pin 1) vdd (pin 8) 0. 01f 10f 3.3v or 2.5v 0.01f vdd (pin 1) vdd (pin 8) 0.01f 10f 10 ? clk 84 ? 84 ? z0 = 50 ? z0 = 50 ? 3.3v 125 ? 125 ? in clk# device xin xout x1 18 pf parallel crystal c1 33 pf c2 27 pf
cy2xp311 document number: 001-59931 rev. *c page 10 of 14 ordering code definitions ordering information part number package type product flow CY2XP311ZXC 8-pin tssop commercial, 0 ? c to 70 ? c CY2XP311ZXCt 8-pin tssop ? tape and reel commercial, 0 ? c to 70 ? c cy2xp311zxi 8-pin tssop industrial, ?40 ? c to 85 ? c cy2xp311zxit 8-pin tssop ? tape and reel industrial, ?40 ? c to 85 ? c x = blank or t blank = tube; t = tape and reel temperature range: x = c or i c = commercial; i = industrial pb-free package type: z = 8-pin tssop part identifier family company id: cy = cypress 2x cy p311 z t x x
cy2xp311 document number: 001-59931 rev. *c page 11 of 14 package drawing and dimensions figure 13. 8-pin tssop (4.40 mm body) package outline, 51-85093 51-85093 *d
cy2xp311 document number: 001-59931 rev. *c page 12 of 14 acronyms document conventions units of measure acronym description clkout clock output cmos complementary metal oxide semiconductor dpm die pick map eprom erasable programmable read only memory lvds low-voltage differential signalling lvpecl low-voltage positive emitter coupled logic ntsc national televisi on system committee oe output enable pal phase alternate line pd power down pll phase locked loop ttl transistor-transistor logic symbol unit of measure c degree celsius khz kilohertz k ? kilohm mhz megahertz m ? megaohm a microampere s microsecond v microvolt vrms microvolts root-mean-square ma milliampere mm millimeter ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt ? ohm ppm parts per million vvolt
cy2xp311 document number: 001-59931 rev. *c page 13 of 14 document history page document title: cy2xp311, 312.5 mhz lvpecl clock generator document number: 001-59931 rev. ecn no. submission date orig. of change description of change ** 2897143 3/22/2010 kvm new data sheet. *a 2915328 04/16/2010 kvm changed status from preliminary to final *b 3201150 03/21/201 1 bash added ordering code definition. updated package drawing and dimensions . added acronyms and units of measure . *c 4335323 04/07/2014 cinm updated package drawing and dimensions : spec 51-85093 ? changed revision from *c to *d. updated in new template. completing sunset review.
document number: 001-59931 rev. *c revised april 7, 2014 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2xp311 ? cypress semiconductor corporation, 2010-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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